To provide asynchronous data from a transmitting entity having a first transmitting frequency to a receiving entity, via wired or wireless transmission media, synchronizing information must be transmitted with the data in order to provide the receiving entity with the appropriate rate at which to receive and process the information. For a continuous data stream, it is extremely difficult to maintain synchronization of the regenerated clock signal at the receiver, due to the inherent instability over time of the standard clocking sources, such as crystal/crystal oscillators. As a consequence, most transmitted information is provided in non-continuous data packets which include not only the information bits but also a headcode having synchronizing bits to synchronize the receiver for processing of the information bits. Receivers generally require central processing units, CPU's, or microprocessors for receiving the synchronization codes and setting the receiver's clocking sources to the synchronization frequency. A high stability clock source is required to maintain the synchronization of receipt of the information to the transmitting rate to prevent loss of data. In addition, synchronization can be adversely affected by hardware time delays and noise encountered along the transmission medium, neither of which can be filtered out or otherwise accounted for by the CPU. Noise spikes cause false triggering of the receiver clock, either prematurely or at mid-transmission, activating the associated processing circuitry to begin processing of received data, which may or may not be any or all of the information data. The synchronization error caused by false triggering will result in loss of the entire data packet if processing is not correctly begun on the first information bit. Errors due to hardware delay and timing source instability contribute to an accumulated error which can affect the processing of more than just a single data packet.
What is required, therefore, is a system which can instantly synchronize the receiver for each transmitted data packet, thereby avoiding the affects of accumulated error. In addition, a means by which correct synchronization can be confirmed instantly will assure that losses are limited to the loss of a single data packet.
It is, therefore, an objective of the present invention to provide a data transmission and recovery system which provides instantaneous synchronization of the receiver upon detection of the first bit of an incoming data packet.
It is another, more specific objective of the present invention to provide a high frequency timing base at the receiver which will allow virtually instantaneous synchronization.
Yet another objective of the present invention is to provide a data transmission and recovery system which does not require a high stability timing source.
Still another objective of the present invention is providing a receiver for asynchronous data receipt and recovery which does not require the use of a microprocessor.
Still another objective of the present invention is to limit the potential losses of data to a single data packet when providing digital data from a transmitting end to a receiving end.